Ferromagnetic liner for conductive lines of magnetic memory cells

ABSTRACT

A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in a plate-up method, and the ferromagnetic liner is selectively formed on the plated conductive lines. The ferromagnetic liner may also be formed over conductive lines and a top portion of vias in a peripheral region of the workpiece.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to the following co-pending and commonlyassigned patent application: U.S. Ser. No. 10/249,528, filed on Apr. 17,2003, entitled, “Magnetically Lined Conductors,” which application ishereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to the fabrication ofsemiconductor devices, and more particularly to the fabrication ofmagnetic memory devices.

BACKGROUND

Semiconductors are used in integrated circuits for electronicapplications, including radios, televisions, cell phones, and personalcomputing devices, as examples. One type of semiconductor device is asemiconductor storage device, such as a dynamic random access memory(DRAM) or flash memory, which use electric charge to store information.

A recent development in semiconductor memory devices involves spinelectronics, which combines semiconductor technology and magnetics. Thespin of electrons, rather than the charge, is used to indicate thepresence of binary states “1” and “0.” One such spin electronic deviceis a magnetic random access memory (MRAM) device, which includesconductive lines (wordlines and bitlines) and a magnetic stack ormagnetic tunnel junction (MTJ), which functions as a magnetic memorycell. A sufficient current flowing through the conductive lines cangenerate enough magnetic field to orient the polarity of the magneticfilms in the magnetic memory cell into a certain direction. Digitalinformation, represented as a “0” or “1,” is storable in the alignmentof magnetic moments in the magnetic memory cell films. The resistance ofthe magnetic memory cell depends on the magnetic moment alignment, andis used as an indicator the binary state of the device.

MRAM devices are typically arranged in an array of rows and columns, andthe wordlines and bitlines are activated to access each individualmemory cell. In a cross-point cell (XPC) MRAM array, current is runthrough the particular wordlines and bitlines to select a particularmagnetic memory cell. In a field effect transistor (FET) array cell,each MTJ is disposed proximate to a FET, and the FET for each MTJ isused to select a particular magnetic memory cell in the array. In a FETarray, an electrode is typically formed between the MTJ and the FET tomake electrical contact between the MTJ and the FET.

An advantage of MRAM devices compared to traditional semiconductormemory devices such as (DRAM) devices is that MRAM devices arenon-volatile. For example, a personal computer (PC) utilizing MRAMdevices would not have a long “boot-up” time as with conventional PCsthat utilize DRAM devices. Also, an MRAM device does not need to becontinually powered to “remember” the stored data. Therefore, it isexpected that MRAM devices will replace flash memory, DRAM and staticrandom access memory devices (SRAM) devices in electronic applicationswhere a low-power, high performance memory device is needed.

Because MRAM devices operate differently than traditional memory devicesand because they are relatively new, they introduce design andmanufacturing challenges.

SUMMARY OF THE INVENTION

Embodiments of the present invention achieve technical advantages byproviding novel methods of forming conductive lines and forming aferromagnetic liner around the conductive lines of an MRAM device.

In accordance with a preferred embodiment of the present invention, amethod of fabricating a conductive line of a magnetic memory deviceincludes providing a workpiece having at least one magnetic memory cellformed thereon, encapsulating the at least one magnetic memory cellwithin a first insulating layer, the at least one magnetic memory cellcomprising an electrical contact disposed thereon, and exposing theelectrical contact of the magnetic memory cell at a top surface of thefirst insulating layer. A plating seed layer is formed upon the firstinsulating layer and the electrical contact over the at least onemagnetic memory cell, a mask is formed over the plating seed layer,leaving an unmasked region above the at least one magnetic memory cell,and a first conductive line is plated in the unmasked regions, includingover the at least one magnetic memory cell. The mask is removed,exposing portions of the plating seed layer, the portions of the platingseed layer exposed by removing the mask are removed, and a ferromagneticliner is formed over at least the first conductive line.

In accordance with another preferred embodiment of the presentinvention, a magnetic memory device includes a plurality of magneticmemory elements formed in an array region and a plurality of conductivevias formed in a peripheral region. A first conductive line is disposedover at least one of the plurality of magnetic memory elements, thefirst conductive line comprising a top surface and sidewalls. A secondconductive line is disposed over at least one of the plurality ofconductive vias, the second conductive line comprising a top surface andsidewalls. A ferromagnetic liner is disposed on the top surface and thesidewalls of the first conductive line, and on the top surface andsidewalls of the second conductive line. The ferromagnetic liner is alsodisposed on a top portion of the sidewalls of a conductive via proximatethe second conductive line.

Advantages of embodiments of the present invention include providingmethods of forming conductive lines and forming ferromagnetic linersaround the conductive lines of MRAM devices. Because ferromagneticliners serve to focus the magnetic field of the conductive wires uponthe memory elements, the same magnitude of field for switching thepolarity of the memory element can be generated with a smaller currentthan for conductive wires without ferromagnetic liners. The writecurrent and power consumption of an MRAM device can be reduced inaccordance with embodiments of the present invention that describe howto create the ferromagnetic liners. Because the conductive lines areplated rather than formed by damascene processes, the conductive linesare free-standing and the ferromagnetic liner can be more easily formedon the top surface and sidewalls thereof into the desired upside-downhorseshoe shape.

The foregoing has outlined rather broadly the features and technicaladvantages of embodiments of the present invention in order that thedetailed description of the invention that follows may be betterunderstood. Additional features and advantages of embodiments of theinvention will be described hereinafter, which form the subject of theclaims of the invention. It should be appreciated by those skilled inthe art that the conception and specific embodiments disclosed may bereadily utilized as a basis for modifying or designing other structuresor processes for carrying out the same purposes of the presentinvention. It should also be realized by those skilled in the art thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a perspective view of a prior art MRAM XPC array; and

FIGS. 2-5, 6A, 6B, 7-9, 10A and 10B show cross-sectional views of amethod of forming a ferromagnetic liner over the top surface andsidewalls of conductive lines of a FET-cell magnetic memory device inaccordance with a preferred embodiment of the present invention.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely an MRAM device. Embodiments ofthe present invention may also be applied, however, to other magneticdevices, namely, magnetic memory devices, for example. Embodiments ofthe invention are also useful in other semiconductor applications whereit is desirable to alter the path of the magnetic field generated byconductive wires.

FIG. 1 illustrates a perspective view of a prior art cross-point MRAMarray 100 having bitlines 122 located substantially perpendicular towordlines 112 in adjacent metallization layers. Magnetic stacks 110 arepositioned between the bitlines 122 and wordlines 112 adjacent andelectrically coupled to bitlines 122 and wordlines 112. The magneticstacks 110 are also referred to herein as magnetic memory elements,magnetic memory cells, or MTJ's.

A typical manufacturing process for the MRAM array 100 of FIG. 1 willnext be described. A workpiece (not shown) is provided, typicallycomprising silicon oxide over single-crystal silicon, for example. Theworkpiece may include other conductive layers or other semiconductorelements, e.g., transistors, diodes, etc. Compound semiconductors suchas GaAs, InP, Si/Ge, and SiC may be used in place of silicon, forexample.

A first inter-level dielectric layer (not shown) is deposited over theworkpiece. The inter-level dielectric may comprise an insulatingmaterial such as silicon dioxide, for example. The inter-leveldielectric layer is patterned, for example, for vias, and etched. Thevias may be filled with a metal such as copper, tungsten or othermetals, for example.

A metallization layer, e.g., an M1 layer comprising aluminum, copper, orother conductive material, is formed next. If copper is used for thefirst conductive lines 112, typically a damascene process is used toform the first conductive lines 112. A dielectric, not shown, isdeposited over inter-level dielectric layer and vias. The dielectriclayer is patterned and etched, and the trenches are filled withconductive material to form the first conductive lines 112 in the M1layer. Alternatively, the first conductive lines 112 may be formed usinga subtractive etch process, and a dielectric material may be disposedbetween the first conductive lines 112.

Next, a magnetic stack 110 is formed over first conductive lines 112.The magnetic stack 110 typically comprises a first magnetic layer 116including one or more magnetic layers. The first magnetic layer 116 maycomprise a plurality of layers of materials such as PtMn, NiMn, IrMn,FeMn, CoFe, Ru, Al, Ta, TaN, and NiFe, as examples, althoughalternatively, other materials may be used for the first magnetic layer116, for example. The first magnetic layer 116 is also referred to as ahard layer, a pinned layer, or a fixed layer because its magneticorientation is fixed. In some situations, it is advantageous to placethe pinned layer in the location of second magnetic layer 120, but forthe purposes of this discussion, 116 is referred to as the pinned layerherein.

The magnetic stack 110 also includes a thin dielectric tunnel barrierlayer 118 comprising an insulator or semiconductor, e.g., Al₂O₃,deposited over the first magnetic layer 116, although alternatively, thedielectric layer 118 may comprise other insulating or semiconductingmaterials. The dielectric layer 118 is often referred to as a tunnellayer or barrier layer.

The magnetic stack 110 also includes a second magnetic layer 120comprising similar materials as the first magnetic layer 116. The secondmagnetic layer 116 is often referred to as the soft layer or free layerbecause its magnetic orientation is changed depending on the desiredlogic state of the magnetic memory cell.

The first magnetic layer 116, dielectric layer 118 and second magneticlayer 120 are patterned to form a plurality of MTJ's 110, with each MTJ110 being disposed over a first conductive line 112. The patternedmagnetic stacks or MTJ's 110 are typically substantially oval in shape,as shown, or alternatively may be other shapes, such as circular,rectangular, or asymmetrically-shaped, as examples. The MTJ's 110comprise magnetic memory elements. The terms “MTJ,” “magnetic memoryelement,” and “magnetic memory cell” are used interchangeably herein.

A plurality of second conductive lines 122 is formed over the MTJ's 110.The second conductive lines 122 may be formed within an M2 layer, forexample, and are typically positioned in a different direction than thefirst conductive lines 112. If the second conductive lines 122 comprisecopper, again, a damascene process is typically used to form them. Adielectric layer (not shown) is deposited over the MTJ's 110. Thedielectric layer is patterned and etched with trenches that will befilled with a conductive material to form the second conductive lines122. Alternatively, a non-damascene process may be used to form thefirst and second conductive lines 112 and 122. Conductive lines 112 and122 may function as the wordlines and bitlines, respectively, of theMRAM array 100, as examples.

The order of the magnetic stack 110 layers may be reversed, e.g., thepinned layer 116 may be on the top of or above the insulating layer 118,and the free layer 120 may be on the bottom of or below the insulatinglayer 118. Similarly, the wordlines 112 and bitlines 122 may be disposedeither above or below the magnetic stack layers 110.

In MRAM devices, information is stored in the free layer 120 of theMTJ's 110. To store the information, the magnetization of oneferromagnetic layer or information layer, e.g., the free layer 120 isaligned either parallel or anti-parallel to a second magnetic layer orreference layer, e.g., the pinned layer 116. The information isdetectable due to the fact that the resistance of a parallel element isdifferent than an anti-parallel element. Switching from a parallel to ananti-parallel state, and vice versa, may be accomplished by runningcurrent, often referred to as the switching current or write current,through one or both conductive lines 112 and 122, and from the pinnedlayer 116 to the free layer 120, or vice versa. The switching currentinduces a magnetic field at the location of the MTJ memory element 110large enough to change the magnetization of the information layer orfree layer 120. A relatively small tunneling current is run through theelement 110 to read the resistive state.

A problem with MRAM devices relates to the amount of current needed inthe conductive lines 122 and 112 to switch the magnetic polarity of theMTJ element 110. Relatively large currents may be needed to induceenough magnetic flux, and this implies a relatively large power neededto operate the memory array. Significant benefits can be realized if theoperating power can be reduced. Therefore, what is needed in the art isa method of focusing or concentrating the magnetic flux of conductive“write” lines onto the magnetic memory elements so that they may switchstate at lower operating power.

Embodiments of the present invention derive technical advantages byproviding a novel method of forming free-standing conductive lines, andforming a ferromagnetic material liner around the conductive lines(e.g., bitlines or wordlines) disposed over a magnetic memory cell. Theferromagnetic liner functions as a barrier layer against materialdiffusion, and also a magnetic flux concentrator.

FIGS. 2-5, 6A, 6B, 7-9, 10A and 10B show cross-sectional views of amethod of forming a ferromagnetic liner over the top surface andsidewalls of conductive lines of a magnetic memory device in accordancewith a preferred embodiment of the present invention. Like numerals areused for the various elements in FIGS. 2-5, 6A, 6B, 7-9, 10A and 10B aswere described with reference to FIG. 1. To avoid repetition, eachreference number shown in the diagram may not necessarily be describedagain in detail herein. Rather, similar materials x10, x12, etc. arepreferably used for the material layers shown as were described for FIG.1, where x=1 in FIG. 1 and x=2 in FIG. 2. Only one MTJ 210 is shown ineach figure; however, there may be a plurality of MTJ's 210 andconductive lines formed on a single device 201.

The embodiments shown in FIGS. 2-5, 6A, 6B, 7-9, 10A and 10B illustratea method of manufacturing a FET MRAM device. However, embodiments of theinvention also have useful application in crosspoint MRAM devices suchas the one shown in FIG. 1.

First, an overview of an embodiment of the invention will be describedwith reference to FIG. 10A. In the cross-sectional view shown in FIG.10A, first conductive lines 212 a, 212 b, and 212 c are formed over aworkpiece 202 and are separated by an insulating layer 204 a. An MTJ 210is formed over the first conductive line 212 a. A conductive cap layeror electrical contact 206 may be formed over the MTJ 210, as shown. TheMTJ 210 may be one of a plurality of MTJ's 210 formed in an MRAM array,such as the one shown in FIG. 1, for example. The MTJ 210 is isolatedelectrically from other MTJ's (not shown) by insulating layers 204 b and204 c.

A second conductive line 240 a comprising a conductive material isformed over the MTJ 210 by plating. A second conductive line 240 b mayalso be formed in a peripheral region of the workpiece 202 over aconductive via 230. A ferromagnetic liner 250 is formed over the secondconductive line 240 a and also over the second conductive line 240 b, asshown.

Because the second conductive lines 240 a and 240 b are formed using aplating technique, they are free-standing and may be selectively coatedwith the ferromagnetic liner 250 using a plating bath, to be describedfurther herein. A process to remove barrier or plating seed materials232 or 234 between adjacent MTJ's 210 is tuned to result in the roundingof the top corners of the conductive lines 240 a and 240 b, whichresults in the rounding of the shape of the ferromagnetic liner 250,enabling better focusing of the magnetic flux generated by currents inconductive lines 240 a and 240 b. The ferromagnetic liner 250 forms theshape of an upside-down letter U in the cross-section of the device 201around the second conductive lines 240 a and 240 b, for example. Abarrier layer 232 may be disposed below the conductive lines 240 a and240 b, and a seed layer 234 may be disposed between the barrier layer232 and the conductive lines 240 a and 240 b, to be described furtherherein.

The second conductive lines 240 a and 240 b may be covered with anencapsulating insulating layer 204 c. The insulating layer 204 ccomprises a dielectric material and may be patterned in subsequentmanufacturing steps to make electrical contact to the second conductiveline 240 a and 240 b, for example (not shown).

Referring to FIG. 2, a manufacturing process for an MRAM device 201 inaccordance with a preferred embodiment of the present invention willnext be described. First, a workpiece 202 comprising a semiconductorsubstrate is provided. The workpiece 202 may include a plurality of FETs203 formed therein, as shown, for example, in a FET MRAM array. Aplurality of first conductive lines 212 a, 212 b and 212 c are formedover the workpiece 202, as shown. The first conductive lines 212 a and212 b may be formed proximate an MTJ 210 in a first metallization layerM1, wherein the first conductive lines 212 a and 212 b are adapted tofunction as wordlines or bitlines of the MRAM device 201, for example.The first conductive lines 212 a, 212 b, and 212 c preferably compriseCu, Ag, Al, or combinations thereof, as examples, although otherconductive materials may alternatively be used. The first conductivelines 212 a, 212 b, and 212 c preferably comprise a thickness of about450 nm or less, although alternatively, the first conductive lines 212a, 212 b, and 212 c may comprise other dimensions. The first conductivelines 212 c may be formed in a peripheral region of the MRAM device 201,e.g., in a region that supplies power or other support circuitry for thedevice 201, as examples. The first conductive line 212 c in theperipheral region may be used to make electrical connection to theworkpiece 202 or to other layers of the device 201, to be describedfurther herein.

An insulating layer 204 a is disposed between the first conductive lines212 a, 212 b and 212 c, as shown. The insulating layer 204 a maycomprise a dielectric material such as SiO₂ or low-k materials, asexamples. A conductive strap 208 may be disposed between one of theconductive lines 212 b and the MTJ 210, as shown, to make electricalcontact between the conductive line 212 b and the MTJ 210. One firstconductive line 212 a in the array region proximate the MTJ 210 may be awrite wordline, and another first conductive line 212 b proximate theMTJ 210 may be a read wordline, as examples.

A cap layer 206 comprising a conductive material may be disposed overthe MTJ 210. The cap layer 206 may comprise a hard mask that was used topattern one or more layers of the MTJ 210, for example. In a preferredembodiment, the cap layer 206 preferably comprises a thickness of about200 nm or less, although alternatively, the cap layer 206 may compriseother dimensions. The cap layer 206 preferably comprises a conductivematerial such as TiN, Ti, Ta, TaN, WN, W, Cu, or combinations thereof,as examples, although the cap layer 206 may alternatively comprise othermaterials. The cap layer 206 may be increased in thickness in accordancewith an embodiment of the invention to provide a larger process windowfor removing a seed layer 234 and barrier layer 232 for secondconductive lines 240 a and 240 b (not shown in FIG. 2; see FIG. 7), tobe described further herein. The cap layer 206 may function as a topelectrical contact for the MTJ 210, for example.

Next, a conductive via 230 (see FIG. 4) is formed over and abutting thefirst conductive line 212 c in the peripheral region of the device 201.The conductive via 230 is preferably formed using a single Damasceneprocess. To form the via 230, an insulating layer 204 b is depositedover the cap layer 206 and insulating layer 204 a, as shown in FIG. 3.The insulating layer 204 b preferably comprises SiO₂, low-k materials,or other insulating materials, as examples. The insulating film 204 b isthen planarized at a height which either exposes the top of theconductive cap 206, or covers the cap 206 by a small enough amount thatthe cap 206 is exposed by the Damascene polish used to pattern via 230.Typical post-planarization height of dielectric film 204 b will bebetween about 50 nm below the top surface of cap 206 and about 10 nmabove the top surface of cap 206, although other heights can beaccommodated by varying subsequent processes, and an alternativeembodiment utilizing thicker dielectric 204 b is explained below.Planarization of the dielectric film 204 b can be accomplished bychemical-mechanical planarization or polish (CMP), etchback techniques,through the use of self-planarizing spin-on dielectrics, or combinationsof these techniques. The insulating layer 204 b may comprise aself-planarizing spin-on dielectric such as SiLK™ available from DuPont,and materials based on methyl silsesquioxane and hydrogen silsesquioxaneor other spin-on dielectric materials, as examples.

In the first embodiment, after planarization of the insulating layer 204b to close proximity with the top surface of cap 206, the insulatinglayer 204 b is etched with a via 230 pattern, and a conductive materialis deposited over the patterned insulating layer 204 b to fill the via,forming conductive via 230. Excess portions of the conductive materialresiding over the insulating layer 204 b are removed, e.g., using anetch or CMP process, leaving the structure shown in FIG. 4 having asubstantially planar top surface 226, and the conductive top surfaces ofboth cap 206 and via 230 are exposed for the next process step.

In an alternative embodiment, preferably the insulating material 204 bis deposited substantially thicker than shown in FIG. 3, so that thelowest level of the upper surface of 204 b is preferably more than about100 nm above the conductive cap 206. Before the insulating layer 204 bis etched with the via 230 pattern, the insulating material 204 b isplanarized using a CMP process that leaves preferably more than about 25nm of insulating material 204 b above the conductive cap 206. At thispoint, the via 230 pattern is etched into dielectric layer 204 b, thevia is filled with conductive material, and is polished in standarddamascene fashion. The top surface of the dielectric layer 204 b issubstantially coplanar with the top surface of via 230, and bothsurfaces are preferably more than about 10 nm above the top surface ofcap 206. To prepare for the deposition of the next conductive wiringlayer, the top surface of cap layer 206 must be exposed. To accomplishthis, the planar top surface of dielectric 204 b is then etched with awet chemical or reactive ion etch (RIE) process so that the cap layer206 is exposed. This may be accomplished with a timed etch, or forbetter process control may use an endpoint signal generated frombyproducts of the cap layer 206 that are exposed to the etch. Thisalternative embodiment is advantageous in that CMP stresses as seen bythe MTJ 210 are greatly reduced through the use of an encapsulatingdielectric that completely covers MTJ 210 and cap layer 206 during anyCMP processes.

Next, second conductive lines 240 a and 240 b (FIG. 6A) are formed in aplate-up process. Referring to FIG. 5, before the conductive wiringmaterial (which may comprise Cu, or other conductive materials) isdeposited, a barrier material 232 comprised of about 20 nm or less ofTa, TaN, WN, TiN, Ru, multiple layers thereof, or combinations thereof,as examples, may be deposited over the patterned insulating layer 204 bto prevent migration of the conductive wiring material. The barrierlayer 232 may alternatively comprise other materials and dimensions.Preferably, the barrier layer 232 thickness is as small as caneffectively be used for inhibition of seed layer 234 or conductivematerial 240 diffusion, as thinner barrier layers 232 will be easier toremove in subsequent process steps. For example, an effective barrierlayer 232 can be deposited with atomic layer deposition (ALD) inthicknesses of approximately 5 nm. In one embodiment, the barrier layer232 comprises a first layer of TaN deposited over the cap layer 206,insulating layer 204 b, and conductive via 230, and a second layer of Tadeposited over the TaN first layer. The barrier layer 232 preventsdiffusion of the seed layer 234 and conductive material 240 (FIG. 6A)into adjacent material layers, such as 206 and 204 b.

To promote satisfactory plating of conductive material 240 (FIG. 6A), aseed layer 234 is deposited over the barrier layer 232, as shown. Theseed layer 234 preferably comprises about 50 nm or less of a conductivematerial, such as Ru, Cu, Ag, or combinations thereof, as examples,although the seed layer 234 may alternatively comprise other materialsand dimensions. The seed layer 234 may be chosen such that it also canfunction as a barrier layer, in which case layers 232 and 234 are oneand the same. Preferably, the seed layer 234 comprises a thickness ofabout 20 nm or less, so that removing the seed layer 234 is easier in alater manufacturing step. Combining the barrier and seed functions intoone material can allow for thinner barrier/seed layers, and will makefor easier subsequent processing steps. This can be realized, e.g., withthe use of a Ru barrier/seed layer. In one embodiment, the seed layer234 comprises the same material as the conductive material of the secondconductive lines 240 a and 240 b, as an example. The seed layer 234 isalso referred to herein as a plating seed layer 234.

An optional anti-reflective coating (ARC) 236 may be deposited over theseed layer 234, as shown in FIG. 5. The ARC 236 may comprise about 60 nmof an organic material, a photoresist that includes a dye, or other ARCmaterials, as examples. The ARC 236 prevents reflections from the seedlayer 234 surface from impacting the lithographic patterning of mask238. A masking material 238 is deposited over the ARC 236, as shown inFIG. 5. The masking material 238 preferably comprises about 400 nm of aphotoresist or an insulating material such as an oxide or nitride, asexamples, although alternatively, other insulating materials anddimensions may be used. For example, the masking material 238 maycomprise SiO_(x), SiN, SiCOH, SiCN, fluorinated SiO_(x), or lowdielectric constant (low-k) materials such as polyarylene (PAE) e.g.,available from Schumacher, or an aromatic hydrocarbon such as SiLK™,available from DuPont, although other low-k or insulating materials mayalso be used.

The masking material 238 is patterned using a lithography technique withthe pattern for second conductive lines 240 a and 240 b, wherein thesecond conductive lines 240 a will function as the bitlines (orwordlines, depending on the MRAM device 201 design) of the device 201.The ARC 236 is opened or removed from the patterned area, using an etchprocess such as a RIE using H₂ plasma, as an example, although otheretch processes may alternatively be used.

Second conductive lines 240 a and 240 b are formed preferably using anelectrochemical plating (ECP) process, as shown in FIG. 6A. For example,the workpiece 202 may be placed in a plating bath, and the conductivematerial 240 a and 240 b is plated onto the exposed seed layer 234. Theconductive material 240 a and 240 b is not plated onto the maskingmaterial 238; the conductive material 240 a and 240 b is selectivelyplated onto the seed layer 234. If the seed layer 234 comprises copper,for example, preferably copper is plated onto the seed layer 234 to formthe conductive lines 240 a and 240 b.

Various plating techniques may be used to form the second conductivelines 240 a and 240 b. In one embodiment, the plating process iselectroless and/or preferably a potentiostatically triggered electrolessprocess, to minimize or avoid potential bridging of electroless depositbetween second conductive lines 240 a and 240 b due to Pd residue thatcan result from the standard Pd activation process used in electrolessplating. If an electroless plating process is used, the magnetic filmplating bath may be neutral (e.g., having a pH of about 6 to 8), oralkaline (e.g., having a pH of about 8 to 14), as examples. Suchelectroless plating processes advantageously enable the use of athinner, e.g., about 20 nm or less, seed layer 234, for example.

In another embodiment, electroplating may be used to form the secondconductive lines 240 a and 240 b, although the seed layer 234 should bethicker, e.g., about 50 nm in this embodiment, to enhance uniformity ofthe plating. Alternatively, a potentiostatic plating process can beused, for example. In one embodiment, the plating bath is preferablyacidic.

Combinations of the plating processes described herein, and otherplating processes, may be also used to form the conductive lines 240 aand 240 b, for example.

The selectively plated conductive lines 240 a and 240 b preferablycomprise a thickness less than the thickness of the mask material, about450 nm or less, of a conductive material such as Cu, Ag, Al, orcombinations thereof, as examples, although alternatively, theconductive lines 240 a and 240 b may comprise other materials anddimensions.

Note that in FIGS. 5, 6A, 7, 8, 9, and 10A, the material layers inregion 228 above the cap layer 206, and the material layers 212 in FIGS.2 through 10B are shown in cross-section for clarity. As the preferreddesign of MRAM circuitry would typically call for wires 240 a to beorthogonal to or positioned in a different direction than wires 212 a,the simplified figures may not correspond exactly to physical MRAMproduct designs. Although some designs may call for wires 240 a and 212a to be oriented as shown in FIG. 10A, the representations shown inFIGS. 6B and 10B are more realistic (but less illuminating). The FIGS.6B and 10B show conductive lines 240 a without the 90 degree rotation ofregion 228 in the other figures, illustrating that the second conductiveline 240 a, seed layer 234 and barrier layer 232 may be positioned atapproximately a 90 degree angle to the first conductive lines 212 a,proximate the MTJ 210. The exact orientation of these conductive linesis not of impact to the present invention, and the processes disclosedherein are suitable for arbitrarily oriented conductive lines.

Continuing with a preferred embodiment of the processing scheme, themasking material 238 and ARC 236 is removed after plating, as shown inFIG. 7. For example, if the masking material 238 comprises resist, theresist may be removed using a wet strip process or an oxygen plasma. Ifthe masking material 238 comprises an insulating material, an etchprocess selective against etching of the metal layers 240 and 234 may beused to remove the masking material 238 and the ARC 236, for example.

The seed layer 234 is removed, using a RIE (e.g., CO/NH₃), and thebarrier layer 232 is also removed, also using a RIE (e.g., Ar/CF₄).Alternatively, other wet chemical or dry etch processes, includingphysical sputtering or ion milling, as examples, may be used to removethe ARC 236, seed layer 234, and barrier layer 232 from between theconductive lines 240 a and 240 b, for example, leaving the structureshown in FIG. 8.

A top portion of the insulating layer 204 b may be eroded when removingthe barrier layer 232 and/or the seed layer 234 and ARC 236, as shown.About 10 nm or more of the insulating layer 204 b may be removed, forexample, leaving a top portion of the cap layer 206 and/or theconductive via 230 exposed, in one embodiment. The workpiece 202 may beexposed to an optional cleaning step, e.g., using H₂ plasma or othercleaning processes, for example.

Note that advantageously, the RIE processes or other etch processes usedto remove the barrier layer 232, and/or seed layer 234 and ARC 236 maybe tuned to erode a top portion 242 and the corners 244 (e.g., wheresidewalls and the top surface meet) of the second conductive lines 240 aand 240 b. In particular, in a preferred embodiment, the etch process toremove the seed layer 234 will remove material at the corners 244 of thesecond conductive lines 240 a and 240 b, because the conductive lines240 are not be immune to the chemical or physical components chosen toremove the ARC 236, seed 234, or barrier 232 layers. This is beneficialbecause a conductive line having curved edges or corners 244 results ina ferromagnetic liner also having curved edges, and a curved structurefunctions better to focus the magnetic flux generated by current runthrough the conductive lines 240.

A ferromagnetic liner 250 is then formed on the sidewalls, top surfaceand curved corners of the second conductive lines 240 a and 240 b, asshown in FIG. 9. Through choice of deposition methods such aselectroless plating, potentiostatically triggered electroless plating,or potentiostatic plating, as examples, the ferromagnetic liner 250 canbe selectively formed on conductive material surfaces including allexposed edges of conductive lines 240 a and 240 b and the sidewalls ofseed layer 234. The ferromagnetic liner 250 may also form on the exposedsidewall portions of the conductive via 230, as shown at 252.Preferably, the ferromagnetic liner 250 is not formed over theinsulating layer 204 b, barrier layer 232 or cap layer 206 over the MTJ210.

The ferromagnetic liner 250 preferably comprises a magnetic material.The ferromagnetic liner 250 preferably comprises Ni, Fe, Co, alloysthereof, P, B, or combinations thereof, as examples, althoughalternatively, the ferromagnetic liner 250 may comprise other materials.In one embodiment, the ferromagnetic liner 250 comprises CoWP, which isadvantageous because a diffusion barrier between the second conductiveline 240 a and 240 b material and the ferromagnetic liner 250 is notrequired, for example. If the conductive line 240 a and 240 b materialcomprises Cu, for example, CoWB or CoWCu may be used for theferromagnetic liner 250 material, if the coercitivity is small, forexample. The ferromagnetic liner 250 preferably comprises a thickness ofabout 50 nm or less, for example, although alternatively, theferromagnetic liner 250 may comprise other dimensions. The ferromagneticliner 250 preferably comprises CoWP, CoWB, CoWCu, NiFe, NiFeP, NiFeB,CoNi, CoNiP, CoNiB, CoNiFe, CoNiFeP, or CoNiFeB in a preferredembodiment of the present invention, with coercivity and permeabilitythe main factors in determining what material and deposition techniquesare to be used. The coercivity and permeability are tuned to be suitablefor best operation of the electronics and magnetics in the MRAMcircuitry.

The ferromagnetic liner 250 is preferably selectively plated onto thesecond conductive lines 240 a and 240 b. For example, the ferromagneticliner 250 may be plated using a standard electroless plating processusing Pd activation, a potentiostatically triggered electroless process,a potentiostatic electroplating process, a galvanostatic platingprocess, or combinations thereof, as examples, although alternatively,other methods may be used to form the ferromagnetic liner 250.Alternatively, with suitable wiring layout to allow current flow tonecessary wiring, electroplating may be used to form the ferromagneticliner 250 around only certain desired portions of wiring 240.

In one embodiment, an electroless plating process using Pd activation isused to form the ferromagnetic liner 250, the workpiece 202 is dipped ina Pd solution. Pd exchanges with the surface atoms of the secondconductive-lines 240 a and 240 b: e.g., if the second conductive lines240 a and 240 b comprise Cu, a few surface atoms of the secondconductive lines 240 a and 240 b exchange with the Pd, which is morenoble than Cu, for example. The Cu atoms dissolve into the Pd solution.The Pd functions as a catalyst for the electroless plating process toform the ferromagnetic liner 250 on the second conductive lines 240 aand 240 b. Some Pd may be adsorbed into the top surface of theinsulating layer 204 b in this embodiment; therefore, the workpiece 202is preferably rinsed after being dipped in the Pd solution, e.g., with awater rinse, to remove any undesired Pd from the top surface of theinsulating layer 204 b, so that the ferromagnetic liner 250 will not beformed over the insulating layer 204 b, which would short the secondconductive lines 240 a and 240 b. In another embodiment, the platingprocess is preferably catalyzed using current, using potentiostatictriggering, (in which electrons initiate the electroless reaction),which is advantageous because there is no chance that Pd will be leftremaining on the top surface of the insulating layer 204 b, preventingbridging or shorting of the conductive lines 204 a and 204 b, forexample.

If electroplating, potentiostatic, galvanostatic, or potentiostaticallytriggered electroless processes are used to form the ferromagnetic liner250, in these embodiments, the second conductive lines 240 a (and othersecond conductive lines disposed over MTJ's 210 in the array, not shown)need to be shorted together for the plating process. This eitherrequires an additional lithography step, to deposit and pattern theshorting material, or alternatively, the ARC 236 and seed layer 234 canbe patterned after the ferromagnetic liner 250 is electroplated onto thesecond conductive lines 240 a. The seed layer 234 can function as theshorting material (providing a short path for the electroplatingprocess), and the ARC 236 protects the seed layer 234 from being platedwith the ferromagnetic liner. 250, for example. However, in thisembodiment, the ferromagnetic liner 250 is preferably plated thickerthan actually required, because a portion of the ferromagnetic liner 250could be consumed during the seed layer 234 etch. Alternatively, theferromagnetic liner 250 may be selectively formed in the desiredthickness, and it can either be protected by an additional photoresistor oxide while the seed layer 234 is etched away from over theinsulating layer 204 b.

If electroplating is used, in one embodiment, no short line to theperipheral conductive line 240 b may be formed, so that the peripheralconductive line 240 b does not get plated with the ferromagnetic liner250 (not shown). This can be advantageous because later when contact ismade to the via 230, there is no magnetic material (e.g., ferromagneticliner 250) present that could contaminate tools.

Note that the ferromagnetic liner 250 is substantially conformal to theshape of the underlying second conductive lines 240 a and 240 b;therefore, the ferromagnetic liner 250 includes a curve where the secondconductive line 240 a and 240 b top surface meets the sidewall, asshown.

The ferromagnetic liner 250 may be deposited using other depositiontechniques, e.g., a selective chemical vapor deposition (CVD) process orother selective deposition methods, or combinations thereof with theabove mentioned plating process. A diffusion barrier (not shown) may beformed or deposited over the second conductive lines 240 a and 240 busing before forming the ferromagnetic liner 250, for example. Thediffusion barrier preferably comprises a material that preventsdiffusion of the second conductive line 240 a and 240 b material intoadjacent material layers yet allows the selective formation of theferromagnetic liner 250 over the second conductive lines 240 a and 240 busing a plating process. For example, the diffusion barrier may compriseCoWP, CoWB, or other Co alloys, as examples, deposited in a thickness ofabout 30 nm or less, although alternatively, the diffusion barrier maycomprise other materials and dimensions. A diffusion barrier may also bedeposited after the ferromagnetic liner 250, if there is concern thatthe ferromagnetic liner material may migrate during subsequentprocessing and device operation.

An insulating layer 204 c is deposited over the ferromagnetic liner 250,exposed portions of the insulating layer 204 b, and exposed edgeportions of the barrier layer 232, as shown in FIG. 10A. FIG. 10B showsregion 228 with a 90-degree rotation, as a more realistic embodiment.

The manufacturing processing of the device 201 is continued with thedeposition of encapsulating insulating layer 204 c. For example, theferromagnetic liner 250 may be encapsulated with a non-conductivediffusion barrier such as a Si:C:H based CVD material or otherdielectric material. Other conductive structures such as vias may beformed in the insulating layers 204 c, 204 b and 204 a. At the site ofthe vias 230, e.g., second conductive line 240 b, flux concentration isnot necessary, but the magnetic materials of the ferromagnetic liner 250does not deleteriously impact the electrical performance of the vias,and can help to prevent void formation by inhibiting material diffusionnear the vias.

The cap layer 206 provides an increased process window for the novelmethod of forming conductive lines 240 a and 240 b and ferromagneticliner 250 in accordance with embodiments of the present invention. Forexample, the cap layer 206 advantageously protects the MTJ 210 duringthe formation of the conductive lines 240 a and 240 b and ferromagneticliner 250. The MTJ 210 is not exposed to the plating or etch processesdescribed herein.

Advantages of embodiments of the invention include providing methods ofincreasing the flux concentration of second conductive lines 240 a of amagnetic memory device 201 by forming free-standing conductive lines 240a, and forming a ferromagnetic liner 250 on the sidewalls, top surfacesand curved corner edges of the second conductive lines 240 a. Becausethe magnetic flux is concentrated, the write current for magnetic memorycell or MTJ 210 may be decreased in accordance with embodiments of thepresent invention, decreasing the power consumption for the memorydevice 201, for example. Alternatively, for the same amount of currentin wire 240 a, the better flux concentration with liner 250 will allowuse of MTJ devices 210 with higher switching field thresholds. This canimprove operating margins, error immunity, and lifetime of the circuit.

Embodiments of the present application are advantageous when implementedin any magnetic memory device, including MRAM device 201, for example.Embodiments of the invention may be implemented in cross-point MRAMarrays, FET MRAM arrays, and hard disk drive read and write heads, forexample. Embodiments of the present invention may also have usefulapplication in other semiconductor device applications whereconcentration of magnetic flux of a conductive line is required, forinstance in the tuning of wire inductance.

Although embodiments of the present invention and their advantages havebeen described in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.For example, it will be readily understood by those skilled in the artthat many of the features, functions, processes, and materials describedherein may be varied while remaining within the scope of the presentinvention. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure of the present invention,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed, thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present invention. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

1. A method of fabricating a conductive line of a magnetic memorydevice, the method comprising: providing a workpiece having at least onemagnetic memory cell formed thereon; encapsulating the at least onemagnetic memory cell within a first insulating layer, the at least onemagnetic memory cell comprising an electrical contact disposed thereon;exposing the electrical contact of the magnetic memory cell at a topsurface of the first insulating layer; forming a plating seed layer uponthe first insulating layer and the electrical contact over the at leastone magnetic memory cell; forming a mask over the plating seed layer,leaving an unmasked region above the at least one magnetic memory cell;plating a first conductive line in the unmasked regions, including overthe at least one magnetic memory cell; removing the mask, exposingportions of the plating seed layer; removing the portions of the platingseed layer exposed by removing the mask; and forming a ferromagneticliner over at least the first conductive line.
 2. The method accordingto claim 1, wherein forming the ferromagnetic liner over the firstconductive line comprises forming the ferromagnetic liner using anelectroless plating process, an electroless plating process using Pdactivation, a potentiostatically triggered electroless process, apotentiostatic electroplating process, a galvanostatic plating process,an electroplating process, a selective chemical vapor deposition (CVD)process, or combinations thereof.
 3. The method according to claim 1,wherein forming the plating seed layer comprises forming about 50 nm orless of Ru, Cu, or Ag, or combinations thereof.
 4. The method accordingto claim 3, wherein removing the plating seed layer comprises a reactiveion etch (RIE) or ion milling.
 5. The method according to claim 4,wherein plating the first conductive line comprises forming a firstconductive line comprising a top surface and sidewalls, wherein cornersare disposed where the top surface meets the sidewalls, wherein removingthe plating seed layer comprises removing a portion of the corners ofthe first conductive line, forming rounded corners on the firstconductive line.
 6. The method according to claim 1, further comprisingforming a barrier layer over the at least one magnetic memory cell,before forming the plating seed layer, and further comprising removingthe barrier layer from over the first insulating layer, before formingthe ferromagnetic liner.
 7. The method according to claim 6, whereinforming the barrier layer comprises forming about 20 nm or less of Ta,TaN, WN, TiN, Ru, or combinations thereof.
 8. The method according toclaim 1, wherein forming the ferromagnetic liner comprises forming about50 nm or less of Ni, Fe, Co, alloys thereof, P, B, or combinationsthereof.
 9. The method according to claim 8, wherein forming theferromagnetic liner comprises forming CoWP, CoWB, CoWCu, NiFe, NiFeP,NiFeB, CoNi, CoNiP, CoNiB, CoNiFe, CoNiFeP, or CoNiFeB.
 10. The methodaccording to claim 1, further comprising forming an anti-reflectivecoating (ARC) over the plating seed layer, before forming the mask, andfurther comprising removing the ARC from over the first insulatinglayer, before forming the ferromagnetic liner.
 11. The method accordingto claim 1, wherein plating the first conductive line comprises forminga first conductive line comprising Cu, Ag, or Al, or combinationsthereof, and wherein plating the first conductive line comprises forminga first conductive line comprising a thickness of about 450 nm or less.12. The method according to claim 1, wherein plating the firstconductive line comprises plating the first conductive line using anelectroless plating process, a potentiostatically triggered electrolessplating process, a potentiostatically triggered electroless platingprocess using Pd activation, an electroplating process, a potentiostaticplating process, or combinations thereof.
 13. The method according toclaim 1, wherein exposing the electrical contact to the magnetic memorycell comprises a chemical-mechanical polish (CMP) of the firstinsulating layer.
 14. The method according to claim 1, wherein exposingthe electrical contact to the magnetic memory cell comprises acombination of a chemical mechanical polish (CMP) process to planarizethe first insulating layer followed by a reactive ion etch (RIE) or wetchemical etch to expose the electrical contact to the magnetic memorycell.
 15. The method according to claim 1, wherein the first insulatinglayer used to encapsulate the memory cell comprises a self-planarizingmaterial, and wherein exposing the top electrical contact to the memorycell is achieved by a reactive ion etch (RIE) or a wet chemical etch ofa portion of the self-planarizing material.
 16. The method according toclaim 1, further comprising: planarizing the first insulating layer; andusing a single damascene process, forming a via in the first insulatinglayer after planarizing the first insulating layer, filling the via inthe first insulating layer with a conductive material, and polishing thefirst insulating layer and the conductive material to form a conductivevia within the first insulating layer; wherein plating the firstconductive line further comprises plating a first conductive line overthe conductive via, and wherein forming the ferromagnetic liner furthercomprises forming the ferromagnetic liner over the first conductive lineover the conductive via.
 17. The method according to claim 16, whereinthe conductive via comprises sidewalls, further comprising removing atop portion of the first insulating layer, before forming theferromagnetic liner, and wherein forming the ferromagnetic liner furthercomprises forming the ferromagnetic liner over a top portion of thesidewalls of the conductive via.
 18. The method according to claim 1,further comprising: planarizing the first insulating layer; and using asingle damascene process, forming a via in the first insulating layerafter planarizing the first insulating layer, filling the via in thefirst insulating layer with a conductive material, and polishing thefirst insulating layer and the conductive material to form a conductivevia within the first insulating layer; wherein plating the firstconductive line further comprises plating a first conductive line overthe conductive via, and wherein forming the ferromagnetic liner does notcomprise forming the ferromagnetic liner over the first conductive lineover the conductive via.
 19. The method according to claim 1, whereinforming the mask comprises forming a resist or forming a dielectricmaterial comprising SiO_(x), SiN, SiCOH, SiCN, fluorinated SiO_(x), or alow dielectric constant (low-k) material.
 20. The method according toclaim 1, wherein the magnetic memory device comprises a magnetic randomaccess memory (MRAM) device, wherein the at least one magnetic memorycell comprises a plurality of magnetic tunnel junctions (MTJ's) arrangedin an array of rows and columns, wherein plating the first conductiveline comprises forming a first conductive line over each of the MTJ's ina row or column of the array.
 21. The method according to claim 1,further comprising planarizing the at least one magnetic memory cell andthe first insulating layer, before forming the mask over the firstinsulating layer.
 22. The method according to claim 21, furthercomprising depositing a second insulating layer over the at least onemagnetic memory cell and the first insulating layer, wherein planarizingthe at least one magnetic memory cell and the first insulating layerfurther comprises planarizing the second insulating layer.
 23. Themethod according to claim 1, wherein the electrical contact disposedover the at least one magnetic memory cell comprises about 200 nm orless of TiN, Ti, Ta, TaN, WN, W, Cu, or combinations thereof.
 24. Themethod according to claim 1, further comprising forming a diffusionbarrier over the first conductive line, before forming the ferromagneticliner.
 25. The method according to claim 24, wherein forming thediffusion barrier comprises forming about 30 nm or less of a Co alloy.26. The method according to claim 24, wherein forming the diffusionbarrier comprises forming CoWP or CoWB.
 27. A magnetic memory device,comprising: a plurality of magnetic memory elements formed in an arrayregion; a plurality of conductive vias formed in a peripheral region,the plurality of conductive vias comprising sidewalls; a firstconductive line disposed over at least one of the plurality of magneticmemory elements, the first conductive line comprising a top surface andsidewalls; a second conductive line disposed over at least one of theplurality of conductive vias, the second conductive line comprising atop surface and sidewalls; and a ferromagnetic liner disposed on the topsurface and the sidewalls of the first conductive line and disposed onthe top surface and sidewalls of the second conductive line, wherein theferromagnetic liner is also disposed on a top portion of the sidewallsof a conductive via proximate the second conductive line.
 28. Themagnetic memory device according to claim 27, wherein the ferromagneticliner comprises about 50 nm or less of Ni, Fe, Co, alloys thereof, P, B,or combinations thereof.
 29. The magnetic memory device according toclaim 28, wherein the ferromagnetic liner comprises CoWP, CoWB, CoWCu,NiFe, NiFeP, NiFeB, CoNi, CoNiP, CoNiB, CoNiFe, CoNiFeP, or CoNiFeB. 30.The magnetic memory device according to claim 27, wherein the firstconductive line and the second conductive line comprise Cu, Ag, Al, orcombinations thereof.
 31. The magnetic memory device according to claim27, further comprising a barrier layer disposed between the firstconductive line and the at least one of the plurality of magnetic memoryelements, and between the second conductive line and the at least one ofthe plurality of conductive vias, and a seed layer disposed between thebarrier layer and the first conductive line, and between the barrierlayer and the second conductive line.
 32. The magnetic memory deviceaccording to claim 31, wherein the barrier layer comprises about 20 nmor less of Ta, TaN, WN, TiN, Ru, or combinations thereof, and whereinthe seed layer comprises about 50 nm or less of Ru, Cu, Ag, orcombinations thereof.
 33. The magnetic memory device according to claim27, wherein the magnetic memory device comprises a magnetic randomaccess memory (MRAM) device, and wherein the plurality of magneticmemory elements comprise magnetic tunnel junctions (MTJ's).
 34. Themagnetic memory device according to claim 27, further comprising adiffusion barrier disposed between the ferromagnetic liner and the firstconductive line, between the ferromagnetic liner and the secondconductive line, and between the ferromagnetic liner and the top portionof the at least one of the plurality of conductive vias.
 35. Themagnetic memory device according to claim 34, wherein the diffusionbarrier comprises about 30 nm or less of CoWP, CoWB, or other Co alloys.